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rev 1.24 11/27/00 characteristics subject to change without notice. 1 of 22 www.xicor.com preliminary information 16k x4163/5 2k x 8 bit cpu supervisor with 16k eeprom features selectable watchdog timer ?ow v cc detection and reset assertion four standard reset threshold voltages adjust low v cc reset threshold voltage using special programming sequence reset signal valid to v cc = 1v low power cmos <20? max standby current, watchdog on <1? standby current, watchdog off 3ma active current 16kbits of eeprom 64-byte page write mode self-timed write cycle 5ms write cycle time (typical) built-in inadvertent write protection power-up/power-down protection circuitry 400khz 2-wire interface 2.7v to 5.5v power supply operation available packages 8-lead soic 8-lead tssop description the x4163/5 combines four popular functions, power-on reset control, watchdog timer, supply voltage supervision, and serial eeprom memory in one package. this combination lowers system cost, reduces board space requirements, and increases reli- ability. applying power to the device activates the power on reset circuit which holds reset /reset active for a period of time. this allows the power supply and oscilla- tor to stabilize before the processor can execute code. the watchdog timer provides an independent protec- tion mechanism for microcontrollers. when the micro- controller fails to restart a timer within a selectable time out interval, the device activates the reset / reset signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the devices low v cc detection circuitry protects the users system from low voltage conditions, resetting the system when v cc falls below the set minimum v cc trip point. reset /reset is asserted until v cc returns to proper operating level and stabilizes. four industry stan- dard v trip thresholds are available, however, xicors unique circuits allow the threshold to be reprogrammed to meet custom requirements or to ?e-tune the thresh- old for applications requiring higher precision. block diagram watchdog timer reset data register command decode & control logic sda scl v cc reset & watchdog timebase power on and generation v trip + - reset (x4163) reset low voltage status register protect logic eeprom array watchdog transition detector wp v cc threshold reset logic block lock control 2kb reset (x4165) s0 s1
x4163/5 ?preliminary information characteristics subject to change without notice. 2 of 22 rev 1.24 11/27/00 www.xicor.com pin configuration s 1 v ss v cc sda scl 3 2 4 1 6 7 5 8 8-pin jedec soic s 0 wp reset /reset v cc s 1 scl reset /reset v ss 3 2 4 1 6 7 5 8 wp sda s 0 8 pin tssop pin function pin (soic) pin (tssop) name function 13 s 0 device select input 24 s 1 device select input 35 reset / reset reset output . reset /reset is an active low/high, open drain output which goes active whenever v cc falls below the minimum v cc sense level. it will remain active until v cc rises above the minimum v cc sense level for 250ms. reset / reset goes active if the watchdog timer is enabled and sda remains either high or low longer than the selectable watchdog time out period. a falling edge on sda, while scl is high, resets the watchdog timer. reset /reset goes ac- tive on power up and remains active for 250ms after the power supply stabilizes. 46 v ss ground 5 7 sda serial data. sda is a bidirectional pin used to transfer data into and out of the de- vice. it has an open drain output and may be wire ored with other open drain or open collector outputs. this pin requires a pull up resistor and the input buffer is always active (not gated). watchdog input. a high to low transition on the sda (while scl is high) restarts the watchdog timer. the absence of a high to low transition within the watchdog time out period results in reset /reset going active. 6 8 scl serial clock. the serial clock controls the serial bus timing for data input and output. 71 wp write protect. wp high used in conjunction with wpen bit prevents writes to the control register. 82 v cc supply voltage
x4163/5 ?preliminary information characteristics subject to change without notice. 3 of 22 rev 1.24 11/27/00 www.xicor.com principles of operation power on reset application of power to the x4163/5 activates a power on reset circuit that pulls the reset /reset pin active. this signal provides several bene?s. it prevents the system microprocessor from starting to operate with insuf?ient voltage. it prevents the processor from operating prior to sta- bilization of the oscillator. it allows time for an fpga to download its con?ura- tion prior to initialization of the circuit. it prevents communication to the eeprom, greatly reducing the likelihood of data corruption on power up. when v cc exceeds the device v trip threshold value for 200ms (nominal) the circuit releases reset / reset allowing the system to begin operation. low voltage monitoring during operation, the x4163/5 monitors the v cc level and asserts reset /reset if supply voltage falls below a preset minimum v trip . the reset /reset signal prevents the microprocessor from operating in a power fail or brownout condition. the reset /reset signal remains active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip for 200ms. watchdog timer the watchdog timer circuit monitors the microproces- sor activity by monitoring the sda and scl pins. the microprocessor must toggle the sda pin high to low periodically, while scl is high (this is a start bit) prior to the expiration of the watchdog time out period to pre- vent a reset /reset signal. the state of two nonvola- tile control bits in the status register determine the watchdog timer period. the microprocessor can change these watchdog bits, or they may be ?ocked by tying the wp pin high. eeprom inadvertent write protection when reset /reset goes active as a result of a low voltage condition or watchdog timer time out, any in- progress communications are terminated. while reset /reset is active, no new communications are allowed and no nonvolatile write operation can start. nonvolatile writes in-progress when reset /reset goes active are allowed to ?ish. additional protection mechanisms are provided with memory block lock and the write protect (wp) pin. these are discussed elsewhere in this document. v cc threshold reset procedure the x4163/5 is shipped with a standard v cc threshold (v trip ) voltage. this value will not change over normal operating and storage conditions. however, in applica- tions where the standard v trip is not exactly right, or if higher precision is needed in the v trip value, the x4163/5 threshold may be adjusted. the procedure is described below, and uses the application of a nonvola- tile control signal. figure 1. set v trip level sequence (v cc = desired v trip values wel bit set) 01234567 scl sda a0h 01234567 00h wp v p = 12-15v 01234567 01h 01234567 00h
x4163/5 ?preliminary information characteristics subject to change without notice. 4 of 22 rev 1.24 11/27/00 www.xicor.com setting the v trip voltage this procedure is used to set the v trip to a higher or lower voltage value. it is necessary to reset the trip point before setting the new value. to set the new v trip voltage, start by setting the wel bit in the control register, then apply the desired v trip threshold voltage to the v cc pin and the programming voltage, v p , to the wp pin and 2 byte address and 1 byte of ?0 data. the stop bit following a valid write operation initiates the v trip programming sequence. bring wp low to complete the operation. resetting the v trip voltage this procedure is used to set the v trip to a ?ative voltage level. for example, if the current v trip is 4.4v and the new v trip must be 4.0v, then the v trip must be reset. when v trip is reset, the new v trip is some- thing less than 1.7v. this procedure must be used to set the voltage to a lower value. to reset the new v trip voltage start by setting the wel bit in the control register, apply v cc and the program- ming voltage, v p , to the wp pin and 2 byte address and 1 byte of ?0 data. the stop bit of a valid write operation initiates the v trip programming sequence. bring wp low to complete the operation. figure 2. reset v trip level sequence (v cc > 3v. wp = 12?5v, wel bit set) figure 3. sample v trip reset circuit 01234567 scl sda a0h 01234567 00h wp v p = 12-15v 01234567 03h 01234567 00h 1 2 3 4 8 7 6 5 x4163 v trip adj. v p reset 4.7k sda scl ? adjust run soic
x4163/5 ?preliminary information characteristics subject to change without notice. 5 of 22 rev 1.24 11/27/00 www.xicor.com figure 4. v trip programming sequence v trip programming apply 5v to v cc decrement v cc reset pin goes active? measured v trip - desired v trip done execute sequence reset v trip set v cc = v cc applied = desired v trip execute sequence set v trip new v cc applied = old v cc applied + error (v cc = v cc - 50mv) execute sequence reset v trip new v cc applied = old v cc applied - error error ?max ?max < error < emax yes no error emax emax = maximum allowed v trip error control register the control register provides the user a mechanism for changing the block lock and watchdog timer set- tings. the block lock and watchdog timer bits are nonvolatile and do not change when power is removed. the control register is accessed at address ffffh. it can only be modi?d by performing a byte write opera- tion directly to the address of the register and only one data byte is allowed for each register write operation. prior to writing to the control register, the wel and rwel bits must be set using a two step process, with the whole sequence requiring 3 steps. see "writing to the control register" below. the user must issue a stop after sending this byte to the register to initiate the nonvolatile cycle that stores wd1, and wd0. the x4163/5 will not acknowledge any data bytes written after the ?st byte is entered. the state of the control register can be read at any time by performing a random read at address ffffh. only one byte is read by each register read operation.
x4163/5 ?preliminary information characteristics subject to change without notice. 6 of 22 rev 1.24 11/27/00 www.xicor.com the x4163/5 resets itself after the ?st byte is read. the master should supply a stop condition to be con- sistent with the bus protocol, but a stop is not required to end this operation. rwel: register write enable latch (volatile) the rwel bit must be set to ? prior to a write to the control register. wel: write enable latch (volatile) the wel bit controls the access to the memory and to the register during a write operation. this bit is a vola- tile latch that powers up in the low (disabled) state. while the wel bit is low, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the data byte). the wel bit is set by writing a ? to the wel bit and zeroes to the other bits of the control register. once set, wel remains set until either it is reset to 0 (by writ- ing a ? to the wel bit and zeroes to the other bits of the control register) or until the part powers up again. writes to the wel bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. wd1, wd0: watchdog timer bits the bits wd1 and wd0 control the period of the watchdog timer. the options are shown below. write protect enable these devices have an advanced block lock scheme that protects one of eight blocks of the array when enabled. it provides hardware write protection through the use of a wp pin and a nonvolatile write protect enable (wpen) bit. four of the 8 protected blocks match the original block lock segments and this pro- tection scheme is fully compatible with the current devices using 2 bits of block lock control (assuming the bp2 bit is set to 0). the write protect (wp) pin and the write protect enable (wpen) bit in the control register control the programmable hardware write protect feature. hard- ware write protection is enabled when the wp pin and the wpen bit are high and disabled when either the wp pin or the wpen bit is low. when the chip is hard- ware write protected, nonvolatile writes as well as to the block protected sections in the memory array cannot be written. only the sections of the memory array that are not block protected can be written. note that since the wpen bit is write protected, it cannot be changed back to a low state; so write protection is enabled as long as the wp pin is held high. 76543210 wpen wd1 wd0 0 0 rwel wel bp2 wd1 wd0 watchdog time out period 0 0 1.4 seconds (factory setting) 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled table 1. write protect enable bit and wp pin function wp wpen memory array not block protected memory array block protected block protect bits wpen bit protection low x writes ok writes blocked writes ok writes ok software high 0 writes ok writes blocked writes ok writes ok software high 1 writes ok writes blocked writes blocked writes blocked hardware
x4163/5 ?preliminary information characteristics subject to change without notice. 7 of 22 rev 1.24 11/27/00 www.xicor.com writing to the control register changing any of the nonvolatile bits of the control reg- ister requires the following steps: write a 02h to the control register to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write. (operation pre- ceeded by a start and ended with a stop). write a 06h to the control register to set both the register write enable latch (rwel) and the wel bit. this is also a volatile cycle. the zeros in the data byte are required. (operation preceeded by a start and ended with a stop). write a value to the control register that has all the control bits set to the desired state. this can be rep- resented as 0xys t 01 r in binary, where xy are the wd bits, and rst are the bp bits. (operation preceeded by a start and ended with a stop). since this is a non- volatile write cycle it will take up to 10ms to com- plete. the rwel bit is reset by this cycle and the sequence must be repeated to change the nonvola- tile bits again. if bit 2 is set to ? in this third step ( 0xys t 11 r ) then the rwel bit is set, but the wd1, wd0, bp2, bp1 and bp0 bits remain unchanged. writing a second byte to the control register is not allowed. doing so aborts the write operation and returns a nack. a read operation occurring between any of the previ- ous operations will not interrupt the register write operation. the rwel bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. to illustrate, a sequence of writes to the device consist- ing of [02h, 06h, 02h] will reset all of the nonvolatile bits in the control register to 0. a sequence of [02h, 06h, 06h] will leave the nonvolatile bits unchanged and the rwel bit remains set. serial interface serial interface conventions the device supports a bidirectional bus oriented proto- col. the protocol de?es any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the devices in this family operate as slaves in all applications. serial clock and data data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. see figure 5. figure 5. valid data changes on the sda bus scl sda data stable data change data stable
x4163/5 ?preliminary information characteristics subject to change without notice. 8 of 22 rev 1.24 11/27/00 www.xicor.com serial start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. see figure 6. serial stop condition all communications must be terminated by a stop condi- tion, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. see figure 6. figure 6. valid start and stop conditions scl sda start stop serial acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 7. the device will respond with an acknowledge after rec- ognition of a start condition and if the correct device identi?r and select bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. the device will acknowledge all incoming data and address bytes, except for the slave address byte when the device identi?r and/or select bits are incorrect. in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. the device will terminate further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. figure 7. acknowledge response from receiver data output from transmitter data output from receiver 8 1 9 start acknowledge scl from master
x4163/5 ?preliminary information characteristics subject to change without notice. 9 of 22 rev 1.24 11/27/00 www.xicor.com serial write operations b yte w rite for a write operation, the device requires the slave address byte and a word address byte. this gives the master access to any one of the words in the array. after receipt of the word address byte, the device responds with an acknowledge, and awaits the next eight bits of data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the mas- ter then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. during this inter- nal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. the sda output is at high impedance. see figure 8. figure 8. byte write sequence s t a r t s t o p slave address word address byte 0 data a c k a c k a c k sda bus signals from the slave signals from the master 0 word address byte 1 a c k 0 1 0 1 a write to a protected block of memory will suppress the acknowledge bit. page write the device is capable of a page write operation. it is initiated in the same manner as the byte write opera- tion; but instead of terminating the write cycle after the ?st data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. after the receipt of each byte, the device will respond with an acknowl- edge, and the address is internally incremented by one. the page address remains constant. when the counter reaches the end of the page, it ?olls over and goes back to ? on the same page. this means that the master can write 64 bytes to the page starting at any location on that page. if the master begins writing at location 60, and loads 12-bytes, then the ?st 4-bytes are written to locations 60 through 63, and the last 8-bytes are written to locations 0 through 7. after- wards, the address counter would point to location 8 of the page that was just written. if the master supplies more than 64-bytes of data, then new data over-writes the previous data, one byte at a time. figure 9. page write operation s t a r t s t o p slave address word address byte 1 data (n) a c k a c k a c k sda bus signals from the slave signals from the master 0 data (1) a c k (1 < n < 64) word address byte 0 a c k 1 0 10
x4163/5 ?preliminary information characteristics subject to change without notice. 10 of 22 rev 1.24 11/27/00 www.xicor.com figure 10. writing 12-bytes to a 64-byte page starting at location 60. address address 60 4 bytes n-1 8 bytes address = 7 address pointer ends here addr = 8 the master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. see figure 9 for the address, acknowledge, and data transfer sequence. stops and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ack is sent, then the device will reset itself without performing the write. the con- tents of the array will not be effected. acknowledge polling the disabling of the inputs during nonvolatile cycles can be used to take advantage of the typical 5ms write cycle time. once the stop condition is issued to indi- cate the end of the masters byte load operation, the device initiates the internal nonvolatile cycle. acknowl- edge polling can be initiated immediately. to do this, the master issues a start condition followed by the slave address byte for a write or read operation. if the device is still busy with the nonvolatile cycle then no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the read or write operation. refer to the ?w chart in figure 11. figure 11. acknowledge polling sequence ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes nonvolatile cycle complete. continue command sequence? issue stop no continue normal read or write command sequence proceed yes
x4163/5 ?preliminary information characteristics subject to change without notice. 11 of 22 rev 1.24 11/27/00 www.xicor.com serial read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address byte is set to one. there are three basic read operations: current address reads, ran- dom reads, and sequential reads. current address read internally the device contains an address counter that maintains the address of the last word read incre- mented by one. therefore, if the last read was to address n, the next read operation would access data from address n+1. on power up, the address of the address counter is unde?ed, requiring a read or write operation for initialization. upon receipt of the slave address byte with the r/w bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. the mas- ter terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. refer to figure 12 for the address, acknowledge, and data transfer sequence. it should be noted that the ninth clock cycle of the read operation is not a ?on? care. to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. figure 12. current address read sequence s t a r t s t o p slave address data a c k sda bus signals from the slave signals from the master 1 0 1 0 1 random read random read operation allows the master to access any memory location in the array. prior to issuing the slave address byte with the r/w bit set to one, the master must ?st perform a ?ummy write operation. the master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. after acknowledging receipts of the word address bytes, the master immediately issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit word. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. refer to figure 13 for the address, acknowledge, and data transfer sequence. figure 13. random address read sequence 0 slave address word address byte 1 a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master word address byte 0 a c k 0 1 0 1
x4163/5 ?preliminary information characteristics subject to change without notice. 12 of 22 rev 1.24 11/27/00 www.xicor.com there is a similar operation, called ?et current address where the device does no operation, but enters a new address into the address counter if a stop is issued instead of the second start shown in figure 13. the device goes into standby mode after the stop and all bus activity will be ignored until a start is detected. the next current address read operation reads from the newly loaded address. this operation could be useful if the master knows the next address it needs to read, but is not ready for the data. sequential read sequential reads can be initiated as either a current address read or random address read. the ?st data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. the device continues to output data for each acknowledge received. the master termi- nates the read operation by not responding with an acknowledge and then issuing a stop condition. the data output is sequential, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one operation. at the end of the address space the counter ?olls over to address 0000 h and the device continues to output data for each acknowledge received. refer to figure 14 for the acknowledge and data transfer sequence. figure 14. sequential read sequence data (2) s t o p slave address data (n) a c k a c k sda bus signals from the slave signals from the master 1 data (n-1) a c k a c k (n is any integer greater than 1) data (1) x4163/5 addressing s lave a ddress b yte following a start condition, the master must output a slave address byte. this byte consists of several parts: a device type identi?r that is ?010 to access the array one bits of ?? next two bits are the device address. one bit of the slave command byte is a r/w bit. the r/w bit of the slave address byte de?es the opera- tion to be performed. when the r/w bit is a one, then a read operation is selected. a zero selects a write operation. refer to figure 15. after loading the entire slave address byte from the sda bus, the device compares the input slave byte data to the proper slave byte. upon a correct com- pare, the device outputs an acknowledge on the sda line. word address the word address is either supplied by the master or obtained from an internal counter. the internal counter is unde?ed on a power up condition.
x4163/5 ?preliminary information characteristics subject to change without notice. 13 of 22 rev 1.24 11/27/00 www.xicor.com figure 15. x4163/5 addressing r/w s0 s1 0 0 1 0 1 slave address byte device identifier device select a8 a9 a10 0 0 0 0 0 word address byte 0?6k high order word address (x4) (x3) (x2) a0 a1 a2 word address byte 0 for all options low order word address (y2) (y1) (y0) a3 (y3) a4 (y4) a5 (y5) a6 (x0) a7 (x1) d0 d1 d2 d3 d4 d5 d6 d7 data byte for all options operational notes the device powers-up in the following state: the device is in the low power standby state. the wel bit is set to ?? in this state it is not possible to write to the device. sda pin is the input mode. reset /reset signal is active for t purst . data protection the following circuitry has been included to prevent inadvertent writes: the wel bit must be set to allow write operations. ? he proper clock count and bit sequence is required prior to the stop bit in order to start a nonvolatile write cycle. a three step sequence is required before writing into the control register to change watchdog timer or block lock settings. the wp pin, when held high, and wpen bit at logic high will prevent all writes to the control register. communication to the device is inhibited while reset /reset is active and any in-progress com- munication is terminated. block lock bits can protect sections of the memory array from write operations. symbol table waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
x4163/5 ?preliminary information characteristics subject to change without notice. 14 of 22 rev 1.24 11/27/00 www.xicor.com absolute maximum ratings temperature under bias ................... -65? to +135? storage temperature ........................ -65? to +150? voltage on any pin with respect to vss ....-1.0v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10 seconds).........300? comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this speci?ation) is not implied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0? 70? industrial -40? +85? option supply voltage limits ?.7 and ?.7a 2.7v to 5.5v blank and ?.5a 4.5v to 5.5v d.c. operating characteristics (over the recommended operating conditions unless otherwise speci?d.) notes: (1) the device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or t wc after a stop ending a write operation. (2) the device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; t wc after a stop that initiates a nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave addr ess byte. (3) v il min. and v ih max. are for reference only and are not tested. symbol parameter v cc = 2.7 to 5.5v unit test conditions min max i cc1 (1) active supply current read 1.0 ma v il = v cc x 0.1, v ih = v cc x 0.9 f scl = 400khz, sda = commands i cc2 (1) active supply current write 3.0 ma i sb (2) standby current dc (wdt off) 1 a v sda = v scl = v sb others = gnd or v sb i sb (2) standby current dc (wdt on) 20 ? v sda =v scl =v sb others = gnd or v sb i li input leakage current 10 ? v in = gnd to v cc i lo output leakage current 10 ? v sda = gnd to v cc device is in standby (2) v il (3) input low voltage -0.5 v cc x 0.3 v v ih (3) input nonvolatile v cc x 0.7 v cc + 0.5 v v hys schmitt trigger input hysteresis fixed input level v cc related level 0.2 .05 x v cc v v v ol output low voltage 0.4 v i ol = 3.0ma (2.7?.5v)
x4163/5 ?preliminary information characteristics subject to change without notice. 15 of 22 rev 1.24 11/27/00 www.xicor.com capacitance (t a = 25?, f = 1.0 mhz, v cc = 5v) notes: (4) this parameter is periodically sampled and not 100% tested. symbol parameter max. unit test conditions c out (4) output capacitance (sda, rst/rst ) 8 pf v out = 0v c in (4) input capacitance (scl, wp) 6 pf v in = 0v equivalent a.c. load circuit a.c. test conditions sda or reset 1533 ? 100pf 5v for v ol = 0.4v and i ol = 3 ma input pulse levels 0.1v cc to 0.9v cc input rise and fall times 10ns input and output timing levels 0.5v cc output load standard output load a.c. characteristics (over recommended operating conditions, unless otherwise specified) notes: (1) typical values are for t a = 25? and v cc = 5.0v (2) cb = total capacitance of one bus line in pf. symbol parameter min. max. unit f scl scl clock frequency 0 400 khz t in pulse width suppression time at inputs 50 ns t aa scl low to sda data out valid 0.1 0.9 ? t buf time the bus free before start of new transmission 1.3 ? t low clock low time 1.3 ? t high clock high time 0.6 ? t su:sta start condition setup time 0.6 ? t hd:sta start condition hold time 0.6 ? t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 ? t dh data output hold time 50 ns t r sda and scl rise time 20 + .1cb 300 ns t f sda and scl fall time 20 + .1cb 300 ns t su:wp wp setup time 0.6 ? t hd:wp wp hold time 0 s cb capacitive load for each bus line 400 pf
x4163/5 ?preliminary information characteristics subject to change without notice. 16 of 22 rev 1.24 11/27/00 www.xicor.com timing diagrams bus timing wp pin timing write cycle timing nonvolatile write cycle timing notes: (1) t wc is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. symbol parameter min. typ. (1) max. unit t wc (1) write cycle time 5 10 ms t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r t hd:wp scl sda in wp t su:wp clk 1 clk 9 slave address byte start scl sda t wc 8th bit of last byte ack stop condition start condition
x4163/5 ?preliminary information characteristics subject to change without notice. 17 of 22 rev 1.24 11/27/00 www.xicor.com power-up and power-down timing reset output timing notes: (8) this parameter is periodically sampled and not 100% tested. sda vs. reset timing symbol parameter min. typ. max. unit v trip reset trip point voltage, x4163/5-4.5a reset trip point voltage, x4163/5 reset trip point voltage, x4163/5-2.7a reset trip point voltage, x4163/5-2.7 4.5 4.25 2.85 2.55 4.62 4.38 2.92 2.62 4.75 4.5 3.0 2.7 v t purst power-up reset time out 100 250 400 ms t rpd (8) v cc detect to reset/output 500 ns t f (8) v cc fall time 100 ? t r (8) v cc rise time 100 ? v rvalid reset valid v cc 1v v cc t purst t r t f t rpd 0 volts v trip reset reset v rvalid (x4165) (x4163) t purst v rvalid t rsp t wdo t rsp >t wdo
x4163/5 ?preliminary information characteristics subject to change without notice. 18 of 22 rev 1.24 11/27/00 www.xicor.com reset output timing v trip programming timing diagram (wel = 1) v trip programming parameters symbol parameter min. typ. max. units t wdo watchdog time out period, wd1 = 1, wd0 = 0 wd1 = 0, wd0 = 1 wd1 = 0, wd0 = 0 (factory setting) 100 450 1 250 650 1.5 400 850 2 ms ms sec t rst reset time out 100 250 400 ms parameter description min. max. unit t vps v trip program enable voltage setup time 1 s t vph v trip program enable voltage hold time 1 s t tsu v trip setup time 1 s t thd v trip hold (stable) time 10 ms t wc v trip write cycle time 10 ms t vpo v trip program enable voltage off time (between successive adjustments) 0 s t rp v trip program recovery period (between successive adjustments) 10 ms v p programming voltage 15 18 v v tran v trip programmed voltage range 2.55 4.75 v v ta1 initial v trip program voltage accuracy (v cc applied? trip ) (programmed at 25?.) -0.1 +0.4 v v ta2 subsequent v trip program voltage accuracy [(v cc applied? ta1 )? trip . programmed at 25?.) -25 +25 mv v tr v trip program voltage repeatability (successive program operations. programmed at 25?.) -25 +25 mv v tv v trip program variation after programming (0?5?). (programmed at 25?.) -25 +25 mv v trip programming parameters are periodically sampled and are not 100% tested. v cc (v trip ) wp t tsu t thd t vph t vps v p v trip t vpo scl sda a0h 01h or 03h t rp 00h 00h
x4163/5 ?preliminary information characteristics subject to change without notice. 19 of 22 rev 1.24 11/27/00 www.xicor.com packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0?- 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in p arentheses in millimeters) 0.250" 0.050"typical 0.050" typical 0.030" typical 8 places footprint
x4163/5 ?preliminary information characteristics subject to change without notice. 20 of 22 rev 1.24 11/27/00 www.xicor.com packaging information note: all dimensions in inches (in p arentheses in millimeters) 8-lead plastic, tssop, package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0??8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical
x4163/5 ?preliminary information characteristics subject to change without notice. 21 of 22 rev 1.24 11/27/00 www.xicor.com ordering information part mark information v cc range v trip range package operating temperature range part number reset (active low) part number reset (active high) 4.5-5.5v 4.5-4.75 8l soic 0??0? x4163s8?.5a x4165s8?.5a -40??5? x4163s8i?.5a x4165s8i?.5a 8l tssop 0??0? x4163v8?.5a x4165v8?.5a -40??5? x4163v8i?.5a x4165v8i?.5a 4.5-5.5v 4.25-4.5 8l soic 0??0? x4163s8 x4165s8 -40??5? x4163s8i x4165s8i 8l tssop 0??0? x4163v8 x4165v8 -40??5? x4163v8i x4165v8i 2.7-5.5v 2.85-3.0 8l soic 0??0? x4163s8?.7a x4165s8?.7a -40??5? x4163s8i?.7a x4165s8i?.7a 8ltssop 0??0? x4163v8?.7a x4165v8?.7a -40??5? x4163v8i?.7a x4165v8i?.7a 2.7-5.5v 2.55-2.7 8l soic 0??0? x4163s8?.7 x4165s8?.7 -40??5? x4163s8i?.7 x4165s8i?.7 8l tssop 0??0? x4163v8?.7 x4165v8?.7 -40??5? x4163v8i?.7 x4165v8i?.7 8-lead tssop eyww xxxxx 8-lead soic/pdip x4163/5 x xx blank = 8-lead soic adb/adk = ?.5a (0 to +70?) add/adm = no suffix (0 to +70?) adf/ado = ?.7a (0 to +70?) adh/adq= ?.7 (0 to +70?) 4163/4165 f = ?.7 (0 to +70?) g = ?.7 (-40 to +85?) blank = no suffix (0 to +70?) i = no suffix (-40 to +85?) an = ?.7a (0 to +70?) ap = ?.7a (-40 to +85?) al = ?.5a (0 to +70?) am = ?.5a (-40 to +85?)
x4163/5 ?preliminary information characteristics subject to change without notice. 22 of 22 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xd cp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2000 patents pending rev 1.24 11/27/00 www.xicor.com

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